US 12,277,088 B2
Multiplexer for selectively connecting a single KVM connection to multiple central processing units
Gary D. Cudak, Raleigh, NC (US); Mehul Shah, Austin, TX (US); Pravin S. Patel, Cary, NC (US); and James Parsonese, Cary, NC (US)
Assigned to Lenovo Enterprise Solutions (Singapore) Pte Ltd., Singapore (SG)
Filed by Lenovo Enterprise Solutions (Singapore) Pte Ltd., Singapore (SG)
Filed on Dec. 22, 2022, as Appl. No. 18/087,152.
Prior Publication US 2024/0211427 A1, Jun. 27, 2024
Int. Cl. G06F 13/42 (2006.01); G06F 13/38 (2006.01)
CPC G06F 13/4221 (2013.01) [G06F 13/382 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multi-processor system, comprising:
first and second central processing units connected by a processor interconnect;
a single baseboard management controller for managing operation of the first and second central processing units, wherein the first and second central processing units are operable as a single unified node;
a single keyboard, video and mouse connection, wherein the single keyboard, video and mouse connection includes a video controller and a USB controller; and
a multiplexer circuit connected to the video controller and the USB controller, wherein the multiplexer circuit includes a selectable PCIe connection to either the first central processing unit or the second central processing unit, a first PCIe multiplexer connected to the video controller and having a selectable PCIe connection to either the first central processing unit or the second central processing unit, and a second PCIe multiplexer connected to the USB controller and having a selectable PCIe connection to either the first central processing unit or the second central processing unit, wherein the first PCIe multiplexer has a first select line input and the second PCIe multiplexer has a second select line input, wherein the baseboard management controller is connected to the first and second select line inputs for communication of the selection signal, and wherein the first and second select line inputs receive the same selection signal to cause the selectable PCIe connections of the first and second PCIe multiplexers to both connect to a selected one of the first and second central processing units.