| CPC G06F 13/28 (2013.01) [G06F 13/1673 (2013.01); G06F 13/24 (2013.01)] | 20 Claims |
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1. A direct memory access architecture for a digital circuit, wherein the direct memory access architecture is applied to the digital circuit in a target device, the target device is connected with a host via a target bus, and the direct memory access architecture comprises: a direct memory access control component, a read data moving component, a write data moving component and a data storage component; wherein the direct memory access control component comprises a control register, a read descriptor storage component, a write descriptor storage component, a read command transfer component and a write command transfer component;
the control register is configured to obtain descriptor address information based on setting from the host;
the read descriptor storage component is configured to store a read descriptor obtained by using the control register;
the write descriptor storage component is configured to store a write descriptor obtained by using the control register;
the read command transfer component is configured to send, to the read data moving component, a read command obtained based on the read descriptor or the descriptor address information;
the write command transfer component is configured to send, to the write data moving component, a write command obtained based on the read descriptor; and
the read data moving component is configured to execute the read command, the write data moving component is configured to execute the write command, and the data storage component is configured to store read data obtained after executing the read command;
wherein the direct memory access control component is configured to receive a moving completion notification sent by the read data moving component and a moving completion notification sent by the write data moving component; and
the direct memory access control component comprises a status updating component, wherein the status updating component is configured to update, upon detecting completion of execution of a target descriptor, target status bit data corresponding to the target descriptor in a system memory of the host;
further comprising a first input first output buffer, wherein the first input first output buffer is configured to buffer read data packets obtained after executing the read command; and
each of the read data packets comprises a data packet tag corresponding to the read command, and the read data packets are arranged in sequence according to the data packet tags of the read data packets to obtain the read data;
wherein the target status bit data in a target status table corresponding to the target descriptor in the host can be updated via a status and interrupt reporting component in a status and interrupt management component.
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