US 12,277,069 B2
Memory address compression within an execution trace
Jordi Mola, Bellevue, WA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Apr. 3, 2024, as Appl. No. 18/625,675.
Application 18/625,675 is a continuation of application No. 18/548,318, granted, now 12,013,793, previously published as PCT/US2022/021092, filed on Mar. 21, 2022.
Claims priority of application No. LU102709 (LU), filed on Mar. 26, 2021.
Prior Publication US 2024/0248856 A1, Jul. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/1045 (2016.01); G06F 11/34 (2006.01); G06F 12/0811 (2016.01)
CPC G06F 12/1045 (2013.01) [G06F 11/3471 (2013.01); G06F 12/0811 (2013.01); G06F 2201/885 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, implemented at a microprocessor that comprises a processing unit, a translation lookaside buffer (TLB) comprising a plurality of TLB slots, and a memory cache comprising a plurality of cache slots, the method comprising:
identifying a TLB entry within one of the plurality of TLB slots, the TLB entry comprising a mapping between a virtual address of a virtual memory page within a virtual address space and a physical address of a physical memory page within a hardware memory;
initiating logging of the TLB entry into an execution trace, including initiating logging of at least (i) the virtual address, and (ii) an identifier for the TLB entry, the identifier uniquely identifying the TLB entry from among a plurality of live entries in the TLB;
subsequent to identifying the TLB entry, identifying a cache entry within one of the plurality of cache slots, the cache entry comprising (i) a physical memory address corresponding to a cache line, and (ii) data of the cache line, the physical memory address comprising a physical memory page identification portion and an offset portion; and
initiating logging of the cache entry into the execution trace, including,
matching the physical memory page identification portion of the physical memory address with the TLB entry, and
based on matching the physical memory page identification portion of the physical memory address with the TLB entry, initiating logging of at least: (i) the identifier for the TLB entry and (ii) the offset portion.