US 12,277,060 B2
Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA)
Sailesh Kumar, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 29, 2021, as Appl. No. 17/334,700.
Application 17/334,700 is a continuation of application No. 16/258,366, filed on Jan. 25, 2019, granted, now 11,023,377.
Claims priority of provisional application 62/634,587, filed on Feb. 23, 2018.
Prior Publication US 2022/0012177 A1, Jan. 13, 2022
Int. Cl. G06F 12/0813 (2016.01); G06F 9/38 (2018.01); G06F 12/0811 (2016.01); G06F 15/78 (2006.01); G06F 30/331 (2020.01); H04L 45/302 (2022.01); H04L 45/586 (2022.01); H04L 45/60 (2022.01); H04L 49/109 (2022.01)
CPC G06F 12/0813 (2013.01) [G06F 9/3838 (2013.01); G06F 12/0811 (2013.01); G06F 15/7807 (2013.01); G06F 30/331 (2020.01); H04L 45/302 (2013.01); H04L 45/586 (2013.01); H04L 45/60 (2013.01); H04L 49/109 (2013.01)] 20 Claims
OG exemplary drawing
 
10. A programmable logic device system, comprising:
programmable logic circuitry; and
a System-on-Chip (SoC) comprising a Network-on-Chip (NoC) having a hardened network topology, wherein the NoC is configured to be configured to share data between endpoints of a plurality of endpoints in the programmable logic circuitry, wherein the NoC is configured to be programmed based on a traffic specification comprising a quality of service (QoS) and a bandwidth requirement of at least a portion of the NoC, wherein the NoC is configured to be reconfigured in accordance with one or more additional traffic specifications, wherein the NoC is configured to be reconfigured to modify one or more functions associated with the NoC, wherein the NoC is configured to be reconfigured by transmitting, to the NoC, mapping information for one or more characteristics associated with the traffic specification, wherein the mapping information comprises one or more routing assignments for two or more NoC layers, and wherein the one or more routing assignments modify a flow of data through the two or more NoC layers, wherein the one or more modified functions are associated with priorities of classes of data, and wherein the NoC comprises:
a plurality of routers, wherein respective routers of the plurality of routers comprise router circuitry to switch data from a first port of the router to a second port of the router;
a plurality of links, wherein respective links of the plurality of links comprise dedicated paths between a first router and a second router of the plurality of routers; and
a plurality of fabric ports, wherein respective fabric ports of the plurality of fabric ports connect the NoC to an endpoint in the programmable logic circuitry.