a substrate,

a host physical interface to memory, the host physical interface including connections for at least one memory channel, the connections for the memory channel including command/address (CA) connections, data connections (DQs), and ECC data/parity connections (ECC DQs), wherein the memory channel includes at least 32 DQs and at least 4 ECC DQs; and

multiple DRAM devices supported by the substrate, the multiple memory devices connected to form at least nine sub-channels, each sub-channel including respective portions of at least two DRAM devices;

wherein memory cells of each sub-channel are independently addressable from memory cells of other sub-channels, and wherein each sub-channel includes at least two data paths, each data path associated with a respective data DQ or ECC DQ;

wherein memory cells of the respective DRAM portions are accessible by local word lines which extend only within the respective DRAM portion, and which are driven by respective sub-word line drivers, and wherein the local word lines being driven by respective sub-word line drivers within the respective DRAM portions serves to limit a number of DQs impacted by a failure of an individual sub-word line driver, and

wherein a bit width of each sub-channel, and independent operability of each DRAM portion, facilitate at least one of error detection and error correction of data in at least a single data path within a sub-channel.