US 12,277,055 B1
Address mapping for a memory system
Jun Zhu, San Jose, CA (US); Toshinao Matsumura, Yokohama (JP); and Gokhan Gultoprak, Dublin (IE)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Feb. 18, 2021, as Appl. No. 17/179,001.
Claims priority of provisional application 62/978,535, filed on Feb. 19, 2020.
Int. Cl. G06F 12/06 (2006.01)
CPC G06F 12/06 (2013.01) [G06F 2212/656 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a system address comprising a first set of bits, wherein the system address is to be mapped to a memory address which has fewer bits than the system address;
partitioning, by using circuitry, the first set of bits into at least a second set of bits and a third set of bits;
determining a fourth set of bits based on the second set of bits, wherein determining the fourth set of bits based on the second set of bits comprises using the second set of bits to index into a table to obtain the fourth set of bits, and wherein the fourth set of bits comprises a first subset of bits that is used as a chip select to select between memory ranks; and
determining the memory address by using the third set of bits and the fourth set of bits, wherein determining the memory address by using the third set of bits and the fourth set of bits comprises:
combining the third set of bits and the fourth set of bits to obtain an address map input;
providing the address map input to a set of two or more address maps;
generating, by the set of two or more address maps, a set of two or more address map outputs based on the address map input; and
selecting an address map output from the set of two or more address map outputs based on one or more bits of the fourth set of bits.