US 12,277,044 B2
System and method for real-time hardware in the loop
Tony Libbrecht, Waregem (BE); Sam De Cock, Bruges (BE); and Christophe De Buyser, Veldegem (BE)
Assigned to DANA BELGIUM N.V., Bruges (BE)
Filed by Dana Belgium N.V., Flanders (BE)
Filed on May 1, 2023, as Appl. No. 18/310,370.
Prior Publication US 2024/0370343 A1, Nov. 7, 2024
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 11/273 (2006.01); H04L 12/40 (2006.01)
CPC G06F 11/273 (2013.01) [G06F 11/1004 (2013.01); H04L 12/40 (2013.01); H04L 2012/40215 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a first computer core including a first group of executable instructions stored in non-transitory memory that include at least a first subset of executable instructions that execute repeatedly at a first time interval that is less than or equal to a predetermined real-time time interval; and
a second computer core, the second computer core different than the first computer core and including a second group of executable instructions stored in non-transitory memory that include at least a second subset of executable instructions that execute repeatedly at a second time interval that is greater than the predetermined real-time time interval.