US 12,277,041 B2
Method for migrating CPU state from an inoperable core to a spare core
James Lewis, San Jose, CA (US); Paul Jordan, Austin, TX (US); Gregory Onufer, Palo Alto, CA (US); and Ali Vahidsafa, Palo Alto, CA (US)
Assigned to Oracle International Corporation, Redwood Shores, CA (US)
Filed by Oracle International Corporation, Redwood Shores, CA (US)
Filed on Jun. 9, 2023, as Appl. No. 18/332,453.
Application 18/332,453 is a continuation of application No. 17/648,443, filed on Feb. 2, 2022, granted, now 11,709,742.
Application 17/648,443 is a continuation of application No. 16/735,564, filed on Jan. 6, 2020, granted, now 11,263,012, issued on Mar. 1, 2022.
Application 16/735,564 is a continuation of application No. 15/632,567, filed on Jun. 26, 2017, granted, now 10,528,351, issued on Jan. 7, 2020.
Application 15/632,567 is a continuation of application No. 14/549,742, filed on Nov. 21, 2014, granted, now 9,710,273, issued on Jul. 18, 2017.
Prior Publication US 2023/0418715 A1, Dec. 28, 2023
Int. Cl. G06F 11/00 (2006.01); G06F 3/06 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 11/20 (2006.01); G06F 12/0815 (2016.01); G06F 12/0875 (2016.01); G06F 12/1027 (2016.01)
CPC G06F 11/2028 (2013.01) [G06F 3/0617 (2013.01); G06F 3/0647 (2013.01); G06F 3/0683 (2013.01); G06F 9/30145 (2013.01); G06F 9/3851 (2013.01); G06F 9/3861 (2013.01); G06F 9/485 (2013.01); G06F 12/0815 (2013.01); G06F 12/0875 (2013.01); G06F 12/1027 (2013.01); G06F 2201/805 (2013.01); G06F 2212/452 (2013.01); Y02D 10/00 (2018.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a set of multi-threaded cores including:
a first core configured to process instructions from a particular thread of a plurality of threads, wherein the first core includes an execution unit and a monitor circuit coupled to the execution unit; and
a second core configured to process instructions of a supervisory thread; and
wherein the monitor circuit is configured to:
determine whether the execution unit is actively committing the instructions;
adjust a count value in response to a determination that no instruction of the particular thread has been committed within a particular time period; and
in response to the adjusted count value satisfying a particular threshold value, assert an alert signal;
wherein the second core is further configured to, in response to the alert signal, halt the first core from further execution of the particular thread; and
wherein the first core is further configured to disable the monitor circuit based on entering an idle state.