| CPC G06F 11/1044 (2013.01) | 14 Claims |
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1. A memory control circuit, comprising:
circuitry configured to:
divide write data and an error correction code for the write data into a plurality of pieces of data;
control each memory of a plurality of memories to execute a write operation of a corresponding piece of data of the plurality of pieces of data;
receive first information indicating one of a success or a failure of the write operation in each memory of the plurality of memories;
transmit a request to each memory of the plurality of memories based on the failure of the write operation in at least one memory of the plurality of memories;
receive a plurality of bit lengths of a plurality of verify errors from the plurality of memories based on the transmitted request,
wherein the plurality of verify errors is associated with the write operation each memory of the plurality of memories;
determine the write operation of the plurality of pieces of data has succeeded, in a case where a total bit length of the plurality of bit lengths is within a range associated with an error bit length tolerance of the error correction code; and
determine the write operation of the plurality of pieces of data has failed, in a case where the total bit length is outside the range.
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