| CPC G06F 11/0793 (2013.01) | 20 Claims |
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9. A method of operating an error correction circuit, the method comprising:
receiving an input clock;
delaying the input clock by a desired time period to generate a delayed clock;
outputting one of the input clock and the delayed clock as an output clock in response to a select signal;
generating output data and latch data based on the output clock and received input data;
detecting a margin error based on the output data and the latch data; and
correcting the margin error, the correcting the margin error including adjusting a level of a select signal based on whether the margin error has been detected.
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