US 12,277,002 B1
Low-latency retimer with seamless clock switchover
Jitendra Mohan, Santa Clara, CA (US); Subbarao Arumilli, Cupertino, CA (US); Charan Enugala, Newark, CA (US); Chi Feng, San Jose, CA (US); Ken (Keqin) Han, Fremont, CA (US); Pulkit Khandelwal, Cupertino, CA (US); Vikas Khandelwal, San Jose, CA (US); Casey Morrison, San Jose, CA (US); Enrique Musoll, San Jose, CA (US); and Vivek Trivedi, Fremont, CA (US)
Assigned to Astera Labs, Inc., Santa Clara, CA (US)
Filed by Astera Labs, Inc., Santa Clara, CA (US)
Filed on Nov. 10, 2023, as Appl. No. 18/506,387.
Application 18/506,387 is a continuation of application No. 17/953,458, filed on Sep. 27, 2022, granted, now 11,853,115.
Application 17/953,458 is a continuation of application No. 17/480,051, filed on Sep. 20, 2021, granted, now 11,487,317, issued on Nov. 1, 2022.
Application 17/480,051 is a continuation of application No. 16/926,614, filed on Jul. 10, 2020, granted, now 11,150,687, issued on Oct. 19, 2021.
Claims priority of provisional application 62/872,321, filed on Jul. 10, 2019.
Int. Cl. G06F 1/06 (2006.01); G06F 1/12 (2006.01); H03K 5/00 (2006.01)
CPC G06F 1/12 (2013.01) [G06F 1/06 (2013.01); H03K 5/00 (2013.01); H03K 2005/00019 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An integrated circuit component comprising:
clock recovery circuitry to generate a first clock signal based on signal transitions within an inbound stream of symbols;
clock-select circuitry responsive to a first control signal to output, as a selected clock signal, the first clock signal during a first time interval and a second clock signal during a second time interval;
alignment-detect circuitry to generate, at least during a third time interval that transpires between the first and second time intervals, a sequence of alignment-detect values that indicate whether the first and second clock signals are in nominal phase alignment; and
switch control circuitry to switch the first control signal from a first state to a second state based on the alignment-detect values such that the selected clock signal is transitioned from one of the first and second clock signals to the other.