	US 12,276,920 B2
	Method for avoiding damage to overlay metrology mark
Chengchang Wei, Shanghai (CN)
Assigned to Shanghai Huali Integrated Circuit Corporation, Shanghai (CN)
Filed by Shanghai Huali Integrated Circuit Corporation, Shanghai (CN)
Filed on Aug. 17, 2022, as Appl. No. 17/889,524.
Claims priority of application No. 202111409279.5 (CN), filed on Nov. 25, 2021.
Prior Publication US 2023/0161268 A1, May 25, 2023
Int. Cl. G03F 7/00 (2006.01); G03F 9/00 (2006.01); H01L 23/544 (2006.01)

CPC G03F 7/70633 (2013.01) [G03F 7/70683 (2013.01); G03F 9/7076 (2013.01); G03F 9/7084 (2013.01); H01L 23/544 (2013.01)]

8 Claims

1. A method for avoiding damage to an overlay metrology mark, at least comprising:

step 1, providing a silicon substrate, the silicon substrate being provided with a scribe line area, forming a plurality of raised silicon structures on an active area of the scribe line area, forming first to third dielectric layers on the silicon structure, and then forming an axial structure of a fin and a spacer attached to a sidewall of the axial structure on the first to third dielectric layers;

step 2, forming a shallow trench isolation (STI) area on the silicon substrate between the axial structures;

step 3, removing a portion of the silicon structure along a height thereof on the scribe line area, wherein a height of the residual silicon structure is 150-300 angstroms higher than that of the STI area;

step 4, forming a plurality of dummy gates on the residual silicon structure on the scribe line, then applying a dielectric layer to fill a gap between the dummy gates, and then polishing the dielectric layer to expose a top of the dummy gate;

step 5, removing the dummy gate to form a groove;

step 6, forming a metal gate in the groove; and

step 7, using the metal gate formed on the residual silicon structure on the scribe line area as an overlay metrology mark for metrology of a subsequently formed metal layer.