US 12,276,890 B2
Display panel having support structures being formed in via holes of the interlayer insulating layer
Binbin Tong, Beijing (CN); Lizhong Wang, Beijing (CN); Jianbo Xian, Beijing (CN); Liping Lei, Beijing (CN); Chunping Long, Beijing (CN); Yunping Di, Beijing (CN); and Ce Ning, Beijing (CN)
Assigned to BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/005,421
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Mar. 30, 2022, PCT No. PCT/CN2022/084072
§ 371(c)(1), (2) Date Jan. 13, 2023,
PCT Pub. No. WO2023/134022, PCT Pub. Date Jul. 20, 2023.
Claims priority of application No. 202210041921.7 (CN), filed on Jan. 14, 2022.
Prior Publication US 2024/0272497 A1, Aug. 15, 2024
Int. Cl. G02F 1/1362 (2006.01); G02F 1/01 (2006.01); G02F 1/1333 (2006.01); G02F 1/1339 (2006.01); G02F 1/1343 (2006.01)
CPC G02F 1/136286 (2013.01) [G02F 1/0107 (2013.01); G02F 1/133308 (2013.01); G02F 1/1339 (2013.01); G02F 1/13396 (2021.01); G02F 1/13439 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a first substrate and a second substrate that are oppositely combined with each other, wherein the first substrate comprises a base substrate, and a gate line, a first electrode, a first interlayer insulating layer, and a second electrode sequentially disposed on the base substrate;
the first interlayer insulating layer comprises a first via hole penetrating through the first interlayer insulating layer, the second electrode is electrically connected to the first electrode through the first via hole, and a first support structure is provided in a region corresponding to the first via hole and on a side of the second electrode away from the base substrate; and
at least a part of the first support structure is located in the first via hole, and an orthographic projection of the first via hole on the base substrate at least partially overlaps with an orthographic projection of the gate line on the base substrate wherein the first substrate is an array substrate, and the array substrate comprises the gate lines and data lines that are provided to be intersected with each other horizontally and vertically on the base substrate, and a plurality of pixel units; each of the plurality of pixel units comprises the first electrode, the second electrode, and the first interlayer insulating layer; the second electrode is in contact with a surface of the first interlayer insulating layer away from the base substrate, and the second electrode extends from an upper surface of the first interlayer insulating layer to a sidewall and a lower opening region of the first via hole and is connected to the first electrode located in the lower opening region; wherein a width d of an opening of the first via hole close to the upper surface of the first interlayer insulating layer satisfies: d≤(K1*M/PPI)*(1−AR*1/(1−Dmin*PPI/M)), and M is a constant value of 25400 μm; PPI is a pixel density, the pixel density is an amount of pixel units per inch, and 1 inch=25400 μm; a width of a single pixel unit is P=M/PPI=25400 μm/PPI, K1 is an aspect ratio of the single pixel unit, AR is an aperture ratio, and Dmin is a limit value of an exposure process.