| CPC G02B 6/136 (2013.01) [G02B 6/12004 (2013.01); G02B 2006/12078 (2013.01)] | 20 Claims |

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1. A method of manufacturing a semiconductor structure, comprising:
(i) depositing a first layer in contact with a first surface area of a substrate, the substrate being of a first semiconductor material and the first layer being of a second semiconductor material;
(ii) depositing a second layer in contact with a second surface area of the substrate, the second surface area substantially co-planar with and outwards of the first surface area, and the second layer being of the first semiconductor material or a third semiconductor material;
(iii) depositing a third layer in contact with the first layer and the second layer, the third layer being of the first semiconductor material or the third semiconductor material or a fourth semiconductor material;
(iv) removing a portion of the third layer to expose a portion of the first layer; and
(v) removing at least a portion of the first layer to create a cavity between the substrate, the second layer and the third layer.
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