US 12,276,706 B2
Multiple stage fuse circuitry for counting failure events
Daniel Joseph Linnen, Limestone, TN (US); Kirubakaran Periyannan, Saratoga, CA (US); and Elliott Peter Rill, San Jose, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 17, 2023, as Appl. No. 18/222,873.
Claims priority of provisional application 63/461,898, filed on Apr. 25, 2023.
Prior Publication US 2024/0361401 A1, Oct. 31, 2024
Int. Cl. G01R 31/50 (2020.01); H02H 3/033 (2006.01); H03K 21/08 (2006.01)
CPC G01R 31/50 (2020.01) [H02H 3/033 (2013.01); H03K 21/08 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of stages of a failure event counting circuit comprising an Nth stage where N refers to an arbitrary stage of the plurality of stages of the failure event counting circuit, the Nth stage comprising:
an Nth fuse trigger circuit configured to receive an event detector signal indicative of a failure event;
an Nth electronic fuse (e-fuse) configured to disconnect a circuit path between a voltage source and a ground in response to the event detector signal; and
an Nth delay circuit coupled to the Nth e-fuse and configured to cause a time delay for activating a subsequent stage of the failure event counting circuit in response to the Nth e-fuse disconnecting,
wherein each of the stages of the failure event counting circuit is configured to use the respective e-fuse to record a discrete failure event.