US 12,276,695 B2
Chip testing method and apparatus
Liang Chen, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Apr. 26, 2022, as Appl. No. 17/660,798.
Claims priority of application No. 202111511707.5 (CN), filed on Dec. 6, 2021.
Prior Publication US 2023/0176113 A1, Jun. 8, 2023
Int. Cl. G01R 31/28 (2006.01)
CPC G01R 31/2882 (2013.01) 18 Claims
OG exemplary drawing
 
1. A chip testing method, comprising:
determining a data receiving window corresponding to each chip to be tested;
determining a time adjustment parameter corresponding to each chip to be tested according to the data receiving window corresponding to each chip to be tested and a data input window preset for a test machine;
determining an actual input time point corresponding to each chip to be tested according to the time adjustment parameter corresponding to each chip to be tested; and
inputting data to each chip to be tested at the actual input time point corresponding to the each chip to be tested, to enable each chip to be tested to receive the data inputted by the test machine in the data receiving window corresponding to the each chip to be tested;
wherein
determining the time adjustment parameter corresponding to each chip to be tested according to the data receiving window corresponding to each chip to be tested and the data input window preset for the test machine comprises:
respectively determining time intervals on a time axis occupied by the data input window preset and the data receiving window corresponding to each chip to be tested; and
determining the time adjustment parameter corresponding to each chip to be tested according to the time intervals on the time axis occupied by the data input window preset and the data receiving window corresponding to each chip to be tested.