| CPC G01R 27/2605 (2013.01) [G01R 27/08 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01)] | 21 Claims |

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1. An apparatus, comprising:
an array of memory cells;
a plurality of access lines, wherein each access line of the plurality of access lines is connected to control gates of a respective plurality of memory cells of the array of memory cells; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to:
apply a reference current to a selected access line of the plurality of access lines;
determine a time difference between a voltage level of a near end of the selected access line being deemed to exceed a first voltage level while applying the reference current, and the voltage level of the near end of the selected access line being deemed to exceed a second voltage level, higher than the first voltage level, while applying the reference current; and
determine a capacitance value of the selected access line in response to a current level of the reference current, the time difference, and a voltage difference between the second voltage level and the first voltage level.
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