wherein the processor, the synchronous signal generation module, the displacement signal conversion circuit, the post-processing circuit, and the Analog-to-Digital conversion module are connected in a closed loop; the synchronous signal generation module, the frequency division circuit, the pulse width modulation module, and the power amplifier are sequentially connected; the processor is further connected with the pulse width modulation module; the pulse width modulation module, the synchronization module, and the Analog-to-Digital conversion module are sequentially connected; the synchronization module is further respectively connected with the synchronous signal generation module and the frequency division circuit;

the synchronous signal generation module is configured to generate a reference signal and send the reference signal to the displacement signal conversion circuit and the frequency division circuit;

the displacement signal conversion circuit is configured to convert the reference signal into an alternating current signal containing displacement information and send the alternating current signal containing the displacement information to the post-processing circuit;

the post-processing circuit is configured to perform post-processing on the alternating current signal containing the displacement information to obtain a standard displacement signal, and send the standard displacement signal to the Analog-to-Digital conversion module;

the frequency division circuit is configured to perform frequency division on the reference signal to generate a frequency division signal and send the frequency division signal to the pulse width modulation module and the synchronization module;

the pulse width modulation module is configured to output a Pulse Width Modulation (PWM) signal to the synchronization module;

the synchronization module is configured to receive the PWM signal from the pulse width modulation module, determine delay time based on a duty ratio of the PWM signal and correspondingly based on the frequency division signal or the PWM signal, and send a synchronization signal based on the delay time to the Analog-to-Digital conversion module, wherein a duration of the delay time is set to be slightly longer than a duration of switching time of the power amplifier, such that during a subsequent Analog-to-Digital conversion, interference of an impulse current and an impulse voltage caused by a device switch in the power amplifier is avoided; and

the Analog-to-Digital conversion module is configured to synchronize with the power amplifier under an action of the synchronization signal, and convert the standard displacement signal into a standard displacement digital signal and send the standard displacement digital signal to the processor, wherein the processor performs data processing on the standard displacement digital signal.