US RE49,913 E1
Vertical power transistor device
Vipindas Pala, San Jose, CA (US); Anant Kumar Agarwal, Chapel Hill, NC (US); Lin Cheng, Chapel Hill, NC (US); Daniel Jenner Lichtenwalner, Raleigh, NC (US); and John Williams Palmour, Cary, NC (US)
Assigned to Wolfspeed, Inc., Durham, NC (US)
Filed by Wolfspeed, Inc., Durham, NC (US)
Filed on Oct. 26, 2020, as Appl. No. 17/080,062.
Application 17/080,062 is a continuation of application No. 15/970,148, filed on May 3, 2018, granted, now RE48380.
Application 15/970,148 is a reissue of application No. 13/962,295, filed on Aug. 8, 2013, granted, now 9,331,197, issued on May 3, 2016.
Application 17/080,062 is a reissue of application No. 13/962,295, filed on Aug. 8, 2013, granted, now 9,331,197, issued on May 3, 2016.
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/108 (2006.01); H01L 21/337 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/94 (2006.01)
CPC H01L 29/0684 (2013.01) [H01L 29/0865 (2013.01); H01L 29/0878 (2013.01); H01L 29/0882 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/7802 (2013.01); H01L 29/7827 (2013.01)] 13 Claims
OG exemplary drawing
 
[ 26. A transistor device comprising:
a substrate;
a drift layer on the substrate;
a spreading layer on the drift layer, the spreading layer comprising a first doping type;
a pair of junction implants that are provided to a first depth in the spreading layer, wherein each of the junction implants in the pair of junction implants comprises:
a well region with a second doping type that is opposite the first doping type; and
a base region with the second doping type;
wherein the well region is provided to the first depth in the spreading layer, and the base region is provided to a second depth in the spreading layer that is less than the first depth; and
a JFET region that is provided to a third depth in the spreading layer that is less than the first depth and less than the second depth;
wherein a thickness of the spreading layer is in a range from 1.0 to 2.5 microns and is provided at a fourth depth that is greater than the first depth, and
wherein a thickness of the JFET region is in a range from 0.75 to 1.5 microns.]