US RE49,912 E1
Semiconductor device
Akihiro Kimura, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Filed by ROHM CO., LTD., Kyoto (JP)
Filed on Jun. 28, 2021, as Appl. No. 17/360,663.
Application 17/360,663 is a continuation of application No. 15/866,825, filed on Jan. 10, 2018, granted, now 10,163,760, issued on Dec. 25, 2018.
Application 15/866,825 is a continuation of application No. 15/265,176, filed on Sep. 14, 2016, granted, now 9,892,996, issued on Feb. 13, 2018.
Application 15/265,176 is a continuation of application No. 14/549,920, filed on Nov. 21, 2014, granted, now 9,484,336, issued on Nov. 1, 2016.
Application 14/549,920 is a continuation of application No. 13/606,581, filed on Sep. 7, 2012, granted, now 8,921,999, issued on Dec. 30, 2014.
Application 17/360,663 is a reissue of application No. 16/185,478, filed on Nov. 9, 2018, granted, now 10,679,927, issued on Jun. 9, 2020.
Claims priority of application No. 2011-195828 (JP), filed on Sep. 8, 2011; application No. 2011-195829 (JP), filed on Sep. 8, 2011; application No. 2011-195830 (JP), filed on Sep. 8, 2011; and application No. 2012-142779 (JP), filed on Jun. 26, 2012.
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 23/433 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/373 (2006.01); H01L 27/02 (2006.01)
CPC H01L 23/49541 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4882 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 23/293 (2013.01); H01L 23/3142 (2013.01); H01L 23/3157 (2013.01); H01L 23/373 (2013.01); H01L 23/3731 (2013.01); H01L 23/4334 (2013.01); H01L 23/49503 (2013.01); H01L 23/49555 (2013.01); H01L 23/49568 (2013.01); H01L 24/73 (2013.01); H01L 27/0211 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/181 (2013.01)] 65 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first island part;
a first semiconductor chip mounted on the first island part;
a second island part;
a second semiconductor chip mounted on the second island part;
a third island part;
a third semiconductor chip mounted on the third island part;
a fourth island part;
a fourth semiconductor chip mounted on the fourth island part;
a fifth semiconductor chip mounted on the fourth island part;
a sixth semiconductor chip mounted on the fourth island part;
a fifth island part;
a first driving semiconductor chip mounted on the fifth island part and connected to each of the first to third semiconductor chips;
a sixth island part;
a second driving semiconductor chip mounted on the sixth island part and connected to each of the fourth to sixth semiconductor chips;
a first lead terminal connected to the first semiconductor chip by a first wire;
a second lead terminal connected to the second semiconductor chip by a second wire;
a third lead terminal connected to the third semiconductor chip by a third wire;
a fourth lead terminal connected to the fourth semiconductor chip by a fourth wire;
a fifth lead terminal connected to the fifth semiconductor chip by a fifth wire;
a sixth lead terminal connected to the sixth semiconductor chip by a sixth wire; and
a seventh lead terminal extending from the fourth island part,
wherein the first to sixth semiconductor chips are arranged in a first direction,
the first lead terminal is longer than the second lead terminal in a second direction perpendicular to the first direction, and
the second lead terminal is longer than the third lead terminal in the second direction [ , and
wherein the first to sixth wires are directly connected to the first to sixth lead terminals, respectively, and the first to sixth wires are electrically connected only between the first to sixth lead terminals and the first to sixth semiconductor chips respectively] .