| CPC H10N 70/826 (2023.02) [G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0038 (2013.01); G11C 13/0069 (2013.01); H10B 63/34 (2023.02); H10N 70/841 (2023.02); H10N 70/8833 (2023.02)] | 15 Claims |
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1. A method of performing a reset operation in a vertical variable resistance memory device comprising a cell string having memory cells disposed in series between a common source line (CSL) and a bit line (BL),
wherein the cell string comprises:
a plurality of word lines spaced apart from one another in a vertical direction;
a vertical gate electrode extending in the vertical direction through the word lines and being insulated from the word lines; and
a channel and a variable resistance pattern disposed between the vertical gate electrode and the word lines, each of the channel and the variable resistance pattern extending in the vertical direction,
wherein the vertical gate electrode and an upper end portion of the channel contact each other and are electrically connected to the BL, and a lower end portion of the channel is electrically connected to the CSL,
wherein each of the memory cells comprises each of the word lines, a portion of the vertical gate electrode facing a corresponding one of the word lines in a horizontal direction, and portions of the channel and the variable resistance pattern between each of the word lines and the portion of the vertical gate electrode facing each other in the horizontal direction,
wherein the method comprises:
applying a third reset voltage to a selected word line among the word lines and 0 V to the vertical gate electrode to form a depletion region at a portion of the channel of a selected memory cell among the memory cells, wherein the selected memory cell comprises the selected word line;
applying a first reset voltage to the vertical gate electrode while maintaining the selected word line at the third reset voltage, wherein the depletion region remains at the portion of the channel of the selected memory cell and oxygen vacancies distributed in a portion of the variable resistance pattern of the selected memory cell move in the horizontal direction to a portion of the variable resistance pattern distal to the channel; and
applying a second reset voltage to the selected word line with the vertical gate electrode at the first reset voltage, wherein the oxygen vacancies distributed in the portion of the variable resistance pattern distal to the channel are arranged in the vertical direction and the selected memory cell is reset.
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