US 11,957,065 B2
Systems and methods for fabrication of superconducting integrated circuits
Shuiyuan Huang, Eagan, MN (US); Byong H. Oh, San Jose, CA (US); Douglas P. Stadtler, Morgan Hill, CA (US); Edward G. Sterpka, Brentwood, CA (US); Paul I. Bunyk, New Westminster (CA); Jed D. Whittaker, Vancouver (CA); Fabio Altomare, North Vancouver (CA); Richard G. Harris, North Vancouver (CA); Colin C. Enderud, Vancouver (CA); Loren J. Swenson, San Jose, CA (US); Nicolas C. Ladizinsky, Burnaby (CA); Jason J. Yao, San Ramon, CA (US); and Eric G. Ladizinsky, Manhattan Beach, CA (US)
Assigned to 1372934 B.C. LTD., Burnaby (CA)
Filed by D-WAVE SYSTEMS INC., Burnaby (CA)
Filed on May 17, 2021, as Appl. No. 17/321,819.
Application 17/321,819 is a continuation of application No. 16/481,788, granted, now 11,038,095, previously published as PCT/US2018/016237, filed on Jan. 31, 2018.
Claims priority of provisional application 62/453,358, filed on Feb. 1, 2017.
Prior Publication US 2021/0384406 A1, Dec. 9, 2021
Int. Cl. H10N 60/01 (2023.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10N 60/85 (2023.01); H10N 69/00 (2023.01)
CPC H10N 60/0156 (2023.02) [H01L 21/76891 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 23/5227 (2013.01); H01L 23/528 (2013.01); H01L 23/53257 (2013.01); H01L 23/53285 (2013.01); H10N 60/85 (2023.02); H10N 69/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a first wiring layer that comprises an electrically conductive material and which resides in a first plane, the first wiring layer comprising a first mark, the first mark having a first set of nominal dimensions and a first resistance specified at least in part by the first set of nominal dimensions;
a second wiring layer that comprises an electrically conductive material and which resides in a second plane which at least partially overlies the first plane, the second wiring layer comprising a second mark, the second mark having second set of nominal dimensions and a second resistance specified at least in part by the second set of nominal dimensions, the second mark having a nominal position along at least one coordinate axis with respect to the first mark; and
a first stud via that comprises an electrically conductive material and which resides in between the first and the second planes, the first stud via having a third set of nominal dimensions and a third resistance specified at least in part by the third set of nominal dimensions, the first stud via which provides a signal path between the first mark and the second mark, the second mark which overlaps the stud via in a first resistive overlap region defined by an orthogonal projection of the second mark on the stud via, the first resistance overlap region having a resistance that is larger than a cumulative resistance of the first mark, the second mark and the stud via at least at temperatures above a critical temperature.