US 11,957,061 B2
Semiconductor device
Hui-Lin Wang, Taipei (TW); Po-Kai Hsu, Tainan (TW); Ju-Chun Fan, Tainan (TW); Yi-Yu Lin, Taichung (TW); Ching-Hua Hsu, Kaohsiung (TW); and Hung-Yueh Chen, Hsinchu (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on May 23, 2023, as Appl. No. 18/200,592.
Application 18/200,592 is a continuation of application No. 17/090,859, filed on Nov. 5, 2020, granted, now 11,700,775.
Claims priority of application No. 202011088594.8 (CN), filed on Oct. 13, 2020.
Prior Publication US 2023/0292627 A1, Sep. 14, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10N 50/10 (2023.01); H10B 61/00 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01)
CPC H10N 50/10 (2023.02) [H10B 61/22 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a first dielectric layer disposed on the substrate, the first dielectric layer around a first metal interconnection;
a second dielectric layer disposed on the first dielectric layer, the second dielectric layer around a via and a second metal interconnection, the second metal interconnection directly contacting the first metal interconnection; and
a third dielectric layer disposed on the second dielectric layer, the third dielectric layer around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection, wherein the third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.