US 11,956,975 B2
BEOL fat wire level ground rule compatible embedded artificial intelligence integration
Soon-Cheon Seo, Glenmont, NY (US); Dexin Kong, Redmond, WA (US); Takashi Ando, Eastchester, NY (US); Paul Charles Jamison, Hopewell Junction, NY (US); Hiroyuki Miyazoe, White Plains, NY (US); Youngseok Kim, Upper Saddle River, NJ (US); Nicole Saulnier, Slingerlands, NY (US); Vijay Narayanan, New York, NY (US); and Iqbal Rashid Saraf, Glenmont, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 16, 2021, as Appl. No. 17/477,039.
Prior Publication US 2023/0079392 A1, Mar. 16, 2023
Int. Cl. H10B 63/00 (2023.01); H01L 23/522 (2006.01); H10N 70/00 (2023.01)
CPC H10B 63/80 (2023.02) [H01L 23/5226 (2013.01); H10N 70/063 (2023.02); H10N 70/8416 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
a resistive random access memory (ReRAM) device area comprising a ReRAM device area first electrically conductive structure embedded in a fat level first interconnect dielectric material layer;
a lower level dielectric cap located beneath the fat level first interconnect dielectric material layer;
a ReRAM device area bottom electrode located on a surface of the ReRAM device area first electrically conductive structure;
a dielectric capping layer located laterally adjacent to the ReRAM device area bottom electrode,
a ReRAM device area ReRAM-containing stack located on the ReRAM device area bottom electrode, wherein the ReRAM device area ReRAM-containing stack comprises a ReRAM device area dielectric switching layer and a ReRAM device area top electrode; and
a ReRAM device area contact structure located above, and in contact with, the ReRAM device area top electrode, wherein the ReRAM device area contact structure has a lower via portion and an upper trench portion.