US 11,956,968 B2
Memory device
Chao-I Wu, Hsinchu County (TW); Yu-Ming Lin, Hsinchu (TW); Sai-Hooi Yeong, Hsinchu County (TW); and Han-Jong Chia, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 10, 2022, as Appl. No. 17/884,578.
Application 17/884,578 is a division of application No. 17/086,463, filed on Nov. 2, 2020.
Claims priority of provisional application 63/040,765, filed on Jun. 18, 2020.
Prior Publication US 2022/0392920 A1, Dec. 8, 2022
Int. Cl. H10B 51/10 (2023.01); H01L 21/28 (2006.01); H01L 23/522 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01)
CPC H10B 51/10 (2023.02) [H01L 23/5226 (2013.01); H01L 29/40111 (2019.08); H01L 29/516 (2013.01); H01L 29/66666 (2013.01); H01L 29/78391 (2014.09); H10B 51/20 (2023.02); H10B 51/30 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a layer stack disposed on a substrate, wherein the layer stack comprises a first dielectric layer, a first source/drain (S/D) layer, a second dielectric layer, and a second S/D layer stacked in order;
a first conductive pillar, penetrating through the layer stack;
a first ferroelectric layer, wrapping the first conductive pillar;
a first channel layer, disposed between the layer stack and the first ferroelectric layer, wherein the first ferroelectric layer is in contact with the first channel layer and the first conductive pillar; and
a first isolation structure, penetrating through in the first conductive pillar to divide the first conductive pillar into two individual first gate pillars, wherein the first isolation structure further divides the first ferroelectric layer into two individual ferroelectric pillars, and divides the first channel layer into two individual channel pillars.