US 11,956,964 B2
Semiconductor memory device and method of manufacturing thereof
Ken Komiya, Nagoya Aichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 12, 2021, as Appl. No. 17/200,283.
Claims priority of application No. 2020-051576 (JP), filed on Mar. 23, 2020.
Prior Publication US 2021/0296328 A1, Sep. 23, 2021
Int. Cl. H01L 27/115 (2017.01); H01L 23/522 (2006.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/35 (2023.02) [H01L 23/5226 (2013.01); H10B 43/27 (2023.02)] 6 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a semiconductor substrate;
a structure including a plurality of insulating films and a plurality of conductive films alternately stacked on the semiconductor substrate; and
a pillar penetrating the structure,
wherein;
the plurality of conductive films include a plurality of first conductive films and a second conductive film arranged closer to the semiconductor substrate than the plurality of first conductive films,
the pillar has a first epitaxial growth layer doped with boron and carbon in a part in contact with the semiconductor substrate, and configured to function as a part of a source side select gate transistor together with the second conductive film,
the plurality of first conductive films are configured to function as a part of a plurality of non-volatile memory cells,
the pillar has a second epitaxial growth layer between the plurality of non-volatile memory cells and the first epitaxial growth layer,
a carbon density of the second epitaxial growth layer is lower than a carbon density of the first epitaxial growth layer, and
a boron density of the second epitaxial growth layer is lower than a boron density of the first epitaxial growth layer.