| CPC H10B 43/27 (2023.02) [H01L 21/02236 (2013.01); H01L 21/02252 (2013.01); H01L 21/30604 (2013.01)] | 12 Claims |
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1. A semiconductor memory device comprising:
a semiconductor substrate;
a first stacked body including a plurality of first insulating layers and a plurality of first conductive layers alternately stacked in a first direction intersecting a surface of the semiconductor substrate;
a second stacked body including a plurality of second insulating layers and a plurality of second conductive layers alternately stacked in the first direction of the first stacked body;
a third insulating layer arranged between the first stacked body and the second stacked body and having a film thickness larger than a film thickness of each of the plurality of first insulating layer and each of the plurality of second insulating layer; and
a pillar penetrating the first stacked body, the third insulating layer, and the second stacked body, the pillar comprising a semiconductor layer extending in the first direction and a charge storage layer extending in the first direction and arranged between the plurality of first conductive layers and the semiconductor layer and between the plurality of second conductive layers and the semiconductor layer, wherein
the pillar has a first region facing one of the plurality of first conductive layers and a connecting part facing the third insulating layer,
a width of the connection part in a second direction orthogonal to the first direction is larger than a width of the first region in the second direction, and
a film thickness of the semiconductor layer at the connection part is larger than a film thickness of the semiconductor layer at the first region.
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