US 11,956,959 B2
Semiconductor memory device and method for manufacturing same
Jun Fujiki, Mie (JP); Shinya Arai, Yokkaichi (JP); and Kotaro Fujii, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on May 24, 2021, as Appl. No. 17/328,030.
Application 17/328,030 is a continuation of application No. 16/928,113, filed on Jul. 14, 2020, granted, now 11,049,878.
Application 16/928,113 is a continuation of application No. 16/129,082, filed on Sep. 12, 2018, granted, now 10,756,104, issued on Aug. 25, 2020.
Claims priority of application No. 2017-247987 (JP), filed on Dec. 25, 2017.
Prior Publication US 2021/0280603 A1, Sep. 9, 2021
Int. Cl. H10B 43/27 (2023.01); H01L 21/768 (2006.01); H01L 27/07 (2006.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/76897 (2013.01); H01L 27/0727 (2013.01); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a semiconductor substrate;
a transistor provided on the semiconductor substrate;
a first interconnection layer provided above the transistor, the first interconnection layer including a first interconnection and a second interconnection, the first interconnection being electrically connected to the semiconductor substrate, the second interconnection being electrically connected to the transistor;
a first conductive layer provided above the first interconnection layer;
a stacked body provided above the first conductive layer and including a plurality of electrode layers stacked in a first direction;
a semiconductor member extending through the stacked body in the first direction and connected to the first conductive layer;
a charge storage member provided between the plurality of electrode layers and the semiconductor member;
a first via provided between the first conductive layer and the first interconnection and connected to the first conductive layer and the first interconnection; and
a second via extending though the stacked body and the first conductive layer and connected to the second interconnection.