US 11,956,954 B2
Electronic devices comprising reduced charge confinement regions in storage nodes of pillars and related methods
Yifen Liu, Boise, ID (US); Yan Song, Singapore (SG); Albert Fayrushin, Boise, ID (US); Naiming Liu, Boise, ID (US); Yingda Dong, Los Altos, CA (US); and George Matamis, Eagle, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 9, 2020, as Appl. No. 17/092,916.
Prior Publication US 2022/0149068 A1, May 12, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 23/522 (2006.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 28 Claims
OG exemplary drawing
 
1. An electronic device comprising:
a stack of alternating dielectric materials and conductive materials arranged in tiers, each of the tiers including a dielectric material and a conductive material vertically neighboring the dielectric material;
a pillar region extending vertically through the stack;
an oxide material comprising a single material composition within the pillar region and laterally adjacent to and directly physically contacting the dielectric materials and the conductive materials of the stack; and
a storage node laterally adjacent to and directly physically contacting the oxide material and within the pillar region, a charge confinement region of the storage node in horizontal alignment with the conductive materials of the stack, and a height of the charge confinement region in a vertical direction less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction.