US 11,956,950 B2
Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
John D. Hopkins, Meridian, ID (US); and Nancy M. Lomeli, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 13, 2022, as Appl. No. 18/080,382.
Application 18/080,382 is a division of application No. 16/807,573, filed on Mar. 3, 2020, granted, now 11,557,597.
Prior Publication US 2023/0114572 A1, Apr. 13, 2023
Int. Cl. H10B 41/27 (2023.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); H01L 21/768 (2006.01); H10B 43/27 (2023.01)
CPC H10B 41/27 (2023.02) [G11C 5/025 (2013.01); G11C 5/06 (2013.01); H01L 21/76838 (2013.01); H10B 43/27 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, the conductive tiers comprising metal;
metal silicide below an uppermost of the insulative tiers and that is directly against and longitudinally-along the metal of individual of the conductive tiers longitudinally-along opposing sides of individual of the memory blocks; and
intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks.