US 11,956,939 B2
Static random access memory using vertical transport field effect transistors
Tsung-Sheng Kang, Ballston Lake, NY (US); Ardasheir Rahman, Schenectady, NY (US); Tao Li, Slingerlands, NY (US); and Albert M. Young, Fishkill, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Mar. 14, 2023, as Appl. No. 18/183,276.
Application 18/183,276 is a continuation of application No. 17/381,462, filed on Jul. 21, 2021, granted, now 11,678,475.
Prior Publication US 2023/0217639 A1, Jul. 6, 2023
Int. Cl. H01L 27/11 (2006.01); H01L 23/528 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H10B 10/00 (2023.01)
CPC H10B 10/12 (2023.02) [H01L 23/5286 (2013.01); H01L 27/092 (2013.01); H01L 29/7827 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of field effect transistor (FET) stacks disposed on separate bottom source/drain (S/D) regions wherein the separate bottom S/D regions are within a substrate, each of the plurality of FET stacks including a vertical transport fin field effect transistor (VTFET) device; and
electrical connections interconnecting gate structures between the VTFET devices such that at least one of the separate bottom S/D regions is laterally adjacent to at least two others of the separate bottom S/D regions at a substrate level.