US 11,956,897 B2
Semiconductor package device and method of manufacturing the same
Ming-Ze Lin, Kaohsiung (TW); Chia Ching Chen, Kaohsiung (TW); and Yi Chuan Ding, Kaohsiung (TW)
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung (TW)
Filed by Advanced Semiconductor Engineering, Inc., Kaohsiung (TW)
Filed on Jul. 25, 2022, as Appl. No. 17/873,088.
Application 17/873,088 is a continuation of application No. 16/888,316, filed on May 29, 2020, granted, now 11,399,429.
Application 16/888,316 is a continuation of application No. 15/621,964, filed on Jun. 13, 2017, granted, now 10,687,419, issued on Jun. 16, 2020.
Prior Publication US 2022/0361326 A1, Nov. 10, 2022
Int. Cl. H05K 1/02 (2006.01); H01L 21/00 (2006.01); H01L 21/48 (2006.01); H01L 21/50 (2006.01); H01L 21/56 (2006.01); H01L 21/66 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/02 (2006.01); H01L 23/13 (2006.01); H01L 23/14 (2006.01); H01L 23/28 (2006.01); H01L 23/31 (2006.01); H01L 23/34 (2006.01); H01L 23/367 (2006.01); H01L 23/42 (2006.01); H01L 23/48 (2006.01); H01L 23/49 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H05K 1/09 (2006.01); H05K 1/11 (2006.01); H05K 3/07 (2006.01); H05K 3/36 (2006.01); H05K 3/46 (2006.01)
CPC H05K 1/0298 (2013.01) [H01L 21/4857 (2013.01); H01L 23/145 (2013.01); H01L 23/49822 (2013.01); H05K 1/115 (2013.01); H05K 3/4623 (2013.01); H01L 2224/16225 (2013.01); H05K 2203/1438 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device package, comprising:
a first dielectric layer having a first surface;
a first interconnection layer disposed over the first surface of the first dielectric layer; and
a first metal layer partially disposed between the first surface of the first dielectric layer and the first interconnection layer;
a second dielectric layer covering the first surface and a lateral surface of the first dielectric layer; and
a first wiring layer disposed within the first dielectric layer, wherein the first wiring layer includes a first portion and a second portion separated from the first portion from a cross-sectional view, and a top surface of the first portion facing the second dielectric layer is free from being exposed by the first dielectric layer,
wherein a lateral end surface of the first metal layer is recessed with respect to a lateral end surface of the first interconnection layer by a first distance,
wherein the lateral surface of the first dielectric layer is recessed with respect to a lateral surface of the second dielectric layer by a second distance, and
wherein the first interconnection layer is disposed directly over the second portion, and a width of the second portion is greater than a width of the first portion.