US 11,956,890 B2
Circuit board and semiconductor module
Yunho Lee, Yongin-si (KR); Yoojeong Kwon, Hwaseong-si (KR); Kyoungsun Kim, Uijeongbu-si (KR); Dongyeop Kim, Hwaseong-si (KR); and Sungjoo Park, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 14, 2022, as Appl. No. 17/720,364.
Claims priority of application No. 10-2021-0113962 (KR), filed on Aug. 27, 2021.
Prior Publication US 2023/0066722 A1, Mar. 2, 2023
Int. Cl. H05K 1/02 (2006.01); H01P 3/08 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); G11C 11/401 (2006.01); G11C 16/04 (2006.01)
CPC H05K 1/0245 (2013.01) [H01P 3/088 (2013.01); H05K 1/115 (2013.01); H05K 1/181 (2013.01); G11C 11/401 (2013.01); G11C 16/0483 (2013.01); H05K 2201/10159 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A circuit board, comprising:
a first insulating layer;
a first wiring pattern and a second wiring pattern each formed to be side to side with each other on an upper surface of the first insulating layer;
a second insulating layer formed on the upper surface of the first insulating layer to cover the first and second wiring patterns;
a third wiring pattern formed on an upper surface of the second insulating layer to overlap the first wiring pattern in a vertical direction;
a fourth wiring pattern formed on the upper surface of the second insulating layer to overlap the second wiring pattern in the vertical direction;
a first via passing through the second insulating layer and connecting the first and fourth wiring patterns; and
a second via passing through the second insulating layer and connecting the second and third wiring patterns,
wherein a line width of the first wiring pattern is different from a line width of the third wiring pattern, and
wherein a line width of the second wiring pattern is different from a line width of the fourth wiring pattern.