CPC H04W 56/001 (2013.01) [H04L 5/001 (2013.01); H04L 5/0048 (2013.01); H04W 4/40 (2018.02); H04W 72/23 (2023.01); H04L 5/0005 (2013.01); H04L 5/0007 (2013.01); H04L 5/0051 (2013.01); H04L 5/0094 (2013.01); H04L 5/0098 (2013.01); H04W 88/02 (2013.01)] | 20 Claims |
1. An apparatus comprising:
memory; and
processing circuitry in communication with the memory, wherein the processing circuitry is configured to:
determine a pre-emption of time-frequency resources for transmission of low latency traffic; and
transmit control signaling that indicates the pre-emption of time-frequency resources via a bitmap, wherein bits of the bitmap are indexed between a least significant bit (LSB) and a most significant bit (MSB), and wherein each bit of the bitmap corresponds to a time partition with no granularity in frequency.
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