CPC H04N 19/537 (2014.11) [H04N 19/119 (2014.11); H04N 19/176 (2014.11)] | 1 Claim |
1. An encoder comprising:
circuitry; and
memory, wherein
when a sub-block encoding is to be performed, the circuitry, using the memory, in operation,
determines a plurality of sub-blocks in a first image block, the plurality of sub-blocks including a first sub-block,
determines a first motion vector for the first sub-block by referring to a first motion vector candidate list,
performs first inter prediction processing on the first sub-block using the first motion vector, and
encodes the first image block using a result of the first inter prediction processing, and
when a partition encoding is to be performed, the circuitry, using the memory, in operation,
determines a plurality of partitions in a second image block, the plurality of partitions including a first partition having a non-rectangular shape,
determines a second motion vector for the first partition by referring to a second motion vector candidate list,
performs second inter prediction processing on the first partition using the second motion vector, and
encodes the second image block using a result of the second inter prediction processing.
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