CPC H04N 19/119 (2014.11) [H04N 19/105 (2014.11); H04N 19/139 (2014.11); H04N 19/157 (2014.11); H04N 19/176 (2014.11); H04N 19/52 (2014.11); H04N 19/70 (2014.11); H04N 19/172 (2014.11); H04N 19/174 (2014.11)] | 20 Claims |
1. A method of video processing, comprising:
performing a conversion between a video block of a video and a bitstream of the video in accordance with a rule that defines a format of syntax elements of the bitstream;
wherein the rule specifies whether indication of use of a first coding mode is signaled or whether to signal the indication of use of a first coding mode is based on use of a second coding mode for the video block;
wherein the first coding mode comprises a geometry partition mode in which the video block corresponding to multiple prediction partitions, an inter-intra coding mode in which a prediction block of the video block is derived from an intra prediction signal and an inter prediction signal, and a sub-block merge coding mode in which the conversion uses derived motion information for each sub-block within the block;
wherein the second coding mode is a merge mode;
wherein the merge mode enables inheriting motion information from a merge candidate in a merge candidate list without a motion vector difference for whole of the video block,
wherein the rule includes a first rule that specifies whether syntax elements signaling multiple coding modes are included in the bitstream and a second rule that specifies an order in which the syntax elements signaling the multiple coding modes are included in the bitstream;
wherein the multiple coding modes include two or more of a geometry partition mode, an inter-intra mode, a sub-block merge mode or a merge with motion vector differencing (MMVD) mode; and
wherein the order is changed in the bitstream at a video unit level based on a coding condition of the video unit, and the coding condition comprises a value of a low delay check flag or a dimension of the video block.
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