US 11,956,342 B2
Reliable link management for a high-speed signaling interconnect
Seema Kumar, Santa Clara, CA (US); and Ish Chadha, San Jose, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Nov. 16, 2022, as Appl. No. 17/988,551.
Claims priority of provisional application 63/294,029, filed on Dec. 27, 2021.
Prior Publication US 2023/0208609 A1, Jun. 29, 2023
Int. Cl. H04L 7/00 (2006.01)
CPC H04L 7/0083 (2013.01) [H04L 7/0012 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a link comprising one or more lanes associated with transmitting data and one or more lanes associated with transmitting a clock signal; and
a device coupled with the link and comprising a receiver, the device to:
receive a signal via the one or more lanes associated with transmitting the clock signal;
determine a number of pulses associated with the signal over a period;
determine the number of pulses associated with the signal fail to satisfy a predetermined condition relating to a specified number of pulses for the period; and
initiate a power-down sequence in response to determining the number of pulses fails to satisfy the predetermined condition relating to the number of pulses for the period.