CPC H04L 5/1469 (2013.01) [H04B 17/336 (2015.01); H04W 56/001 (2013.01)] | 26 Claims |
1. An adaptive time-division duplexed (TDD) communications synchronization circuit, comprising:
a power detector circuit configured to:
receive a TDD downlink communications signal formatted for a TDD communication frame comprising a TDD downlink time period and a TDD uplink time period on a TDD downlink communications link;
detect a noise signal level on the TDD downlink communications link over a defined duration of the TDD communication frame that covers at least a portion of the TDD uplink time period;
set a noise threshold floor level for the TDD downlink communications link based on the detected noise signal level in the TDD uplink time period of the TDD communication frame;
detect the TDD downlink communications signal exceeding the noise threshold floor level; and
detect the TDD downlink time period in the TDD communication frame based on the detect the TDD downlink communications signal exceeding the noise threshold floor level; and
a downlink/uplink switch circuit coupled to an input/output node, the downlink downlink/uplink switch circuit configured to pass the detected TDD downlink communications signal to the input/output node during the detected TDD downlink time period.
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