CPC H04L 25/03305 (2013.01) | 15 Claims |
1. An apparatus comprising:
at least one processor; and
at least one non-transitory memory including computer program code;
the at least one non-transitory memory and the computer program code are configured to, with the at least one processor, cause the apparatus to:
receive a signal from a further apparatus, the signal corresponding to a group of symbols transmitted from the further apparatus;
determine, with performing lattice reduction linear detection on the signal,
a first group of estimated symbols for the group of symbols;
perform, based on a matrix characterizing a channel used to transmit the group of symbols from the further apparatus to the apparatus, the lattice reduction linear detection on the signal;
determine, with performing iterative interference cancellation on the first group of estimated symbols, a second group of estimated symbols for the group of symbols; and
generate, based on the second group of estimated symbols, soft-decision information about the group of symbols for use with a decoder at the apparatus.
|