US 11,955,991 B2
Apparatuses and methods for pipelining memory operations with error correction coding
Wei Bing Shang, Shanghai (CN); Yu Zhang, Shanghai (CN); Hong Wen Li, Shanghai (CN); Yu Peng Fan, Shanghai (CN); Zhong Lai Liu, Shanghai (CN); En Peng Gao, Shanghai (CN); and Liang Zhang, Shanghai (CN)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Apr. 18, 2022, as Appl. No. 17/723,277.
Application 17/723,277 is a division of application No. 16/593,479, filed on Oct. 4, 2019, granted, now 11,309,919.
Application 16/593,479 is a division of application No. 14/423,343, granted, now 10,447,316, issued on Oct. 15, 2019, previously published as PCT/CN2014/009433, filed on Dec. 19, 2014.
Prior Publication US 2022/0247430 A1, Aug. 4, 2022
Int. Cl. H03M 13/45 (2006.01); G06F 9/00 (2006.01); G06F 9/38 (2018.01); G06F 11/10 (2006.01); H03M 13/00 (2006.01)
CPC H03M 13/45 (2013.01) [G06F 9/38 (2013.01); G06F 11/1048 (2013.01); H03M 13/611 (2013.01)] 11 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first error correcting code (ECC) circuit coupled to a memory array and configured to:
receive first data and second data;
correct an error in the first data if detected to provide corrected first data, and if an error is not detected, provide the first data as the corrected first data; and
merge the corrected first data with the second data to provide merged data;
a second ECC circuit coupled to the memory array and configured to:
receive the first data and the second data;
merge the first data and the second data to provide initial merge data while the first ECC circuit is merging the corrected first, data with the second data; and
generate second parity data from the initial merge data; and
a write circuit coupled to the first and second ECC circuits and configured to output the merged data and the second parity data to the memory array.