US 11,955,979 B2
Partial-fractional phase-locked loop with sigma delta modulator and finite impulse response filter
Reetika K Agarwal, Sunnyvale, CA (US); Abbas Komijani, Mountain View, CA (US); and Hongrui Wang, San Jose, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jun. 8, 2022, as Appl. No. 17/835,292.
Prior Publication US 2023/0403013 A1, Dec. 14, 2023
Int. Cl. H03L 7/00 (2006.01); H03C 3/09 (2006.01); H03L 7/089 (2006.01); H03L 7/091 (2006.01); H03L 7/099 (2006.01); H03L 7/185 (2006.01); H03L 7/197 (2006.01); H04L 7/033 (2006.01)
CPC H03L 7/0891 (2013.01) [H03C 3/0941 (2013.01); H03L 7/091 (2013.01); H03L 7/099 (2013.01); H03L 7/185 (2013.01); H03L 7/1976 (2013.01); H04L 7/033 (2013.01)] 17 Claims
OG exemplary drawing
 
1. Phase-locked loop circuitry comprising:
a phase frequency detector having a first input configured to receive a reference clock signal, a second input, and an output;
charge pump and loop filter circuitry having an input coupled to the output of the phase frequency detector and having an output;
a voltage-controlled oscillator having an input coupled to the output of the charge pump and loop filter circuitry and having an output;
a frequency divider having an input coupled to the output of the voltage-controlled oscillator and having an output coupled to the second input of the phase frequency detector;
a first order sigma delta modulator having an output, wherein the first order sigma delta modulator is non-dithered; and
a finite impulse response filter having an input coupled to the output of the first order sigma delta modulator and having an output coupled to the frequency divider.