US 11,955,976 B2
Quadrant alternate switching phase interpolator and phase adjustment method
Yao-Chia Liu, Hsinchu (TW); and Yuan-Sheng Lee, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Oct. 26, 2022, as Appl. No. 17/973,706.
Claims priority of application No. 110140265 (TW), filed on Oct. 29, 2021.
Prior Publication US 2023/0136927 A1, May 4, 2023
Int. Cl. H03K 5/00 (2006.01); H03K 5/131 (2014.01); H03K 5/135 (2006.01); H03K 5/15 (2006.01); H03K 19/173 (2006.01)
CPC H03K 5/135 (2013.01) [H03K 5/131 (2013.01); H03K 5/15093 (2013.01); H03K 19/1737 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A quadrant alternate switching phase interpolator, comprising:
a first multiplexer circuit configured to output one of a first clock signal and a second clock signal to be a first signal in response to a first bit and a third bit in a quadrant control code, wherein the first clock signal and the second clock signal are different in phase by 180 degrees;
a second multiplexer circuit configured to output one of a third clock signal and a fourth clock signal to be a second signal in response to a second bit and a fourth bit in the quadrant control code, wherein the third clock signal and the fourth clock signal are different in phase by 180 degrees, and the first clock signal and the third clock signal are different in phase by 90 degrees;
a phase interpolator circuitry configured to generate an output clock signal in response to the first signal, the second signal, and a plurality of phase control bits; and
a controller circuitry configured to output the quadrant control code and the plurality of phase control bits and perform a bit-shift operation on the plurality of phase control bits to adjust a phase of the output clock signal.