CPC H03K 17/693 (2013.01) [H03F 3/72 (2013.01); H03K 17/005 (2013.01); H03K 17/102 (2013.01)] | 18 Claims |
1. A circuit comprising:
a plurality of inputs;
a plurality of switch assemblies including a first switch assembly, a second switch assembly, and a third switch assembly; and
a buffer including an input and an output,
wherein:
each of the plurality of switch assemblies includes:
a first switch coupled between a respective input of the plurality of inputs and an internal node;
a second switch coupled to the internal node; and
a third switch directly coupled to the internal node;
the input of the buffer is coupled to the respective second switches of the first, second, and third switch assemblies;
and
the output of the buffer is coupled to the respective third switches of the second and third switch assemblies instead of the first switch assembly.
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