US 11,955,932 B2
Cascode amplifier bias circuits
Jonathan James Klaren, San Diego, CA (US); David Kovac, Arlington Heights, IL (US); Eric S. Shapiro, San Diego, CA (US); Christopher C. Murphy, Lake Zurich, IL (US); Robert Mark Englekirk, Littleton, CO (US); Keith Bargroff, San Diego, CA (US); and Tero Tapio Ranta, San Diego, CA (US)
Assigned to pSemi Corporation, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on May 23, 2023, as Appl. No. 18/322,166.
Application 17/843,372 is a division of application No. 16/935,999, filed on Jul. 22, 2020, granted, now 11,374,540, issued on Jun. 28, 2022.
Application 16/935,999 is a division of application No. 16/250,889, filed on Jan. 17, 2019, granted, now 10,756,678, issued on Aug. 25, 2020.
Application 16/250,889 is a division of application No. 15/268,229, filed on Sep. 16, 2016, granted, now 10,250,199, issued on Apr. 2, 2019.
Application 18/322,166 is a continuation of application No. 17/843,372, filed on Jun. 17, 2022, granted, now 11,664,769.
Prior Publication US 2023/0387864 A1, Nov. 30, 2023
Int. Cl. H03F 1/22 (2006.01); H03F 1/30 (2006.01); H03F 1/56 (2006.01); H03F 3/19 (2006.01); H03F 3/193 (2006.01); H03F 3/195 (2006.01); H03F 3/213 (2006.01); H03F 3/24 (2006.01)
CPC H03F 1/223 (2013.01) [H03F 1/301 (2013.01); H03F 1/56 (2013.01); H03F 3/193 (2013.01); H03F 3/195 (2013.01); H03F 3/213 (2013.01); H03F 3/245 (2013.01); H03F 2200/102 (2013.01); H03F 2200/105 (2013.01); H03F 2200/165 (2013.01); H03F 2200/18 (2013.01); H03F 2200/21 (2013.01); H03F 2200/222 (2013.01); H03F 2200/225 (2013.01); H03F 2200/243 (2013.01); H03F 2200/294 (2013.01); H03F 2200/297 (2013.01); H03F 2200/301 (2013.01); H03F 2200/306 (2013.01); H03F 2200/387 (2013.01); H03F 2200/391 (2013.01); H03F 2200/399 (2013.01); H03F 2200/42 (2013.01); H03F 2200/451 (2013.01); H03F 2200/48 (2013.01); H03F 2200/489 (2013.01); H03F 2200/492 (2013.01); H03F 2200/498 (2013.01); H03F 2200/555 (2013.01); H03F 2200/61 (2013.01); H03F 2200/78 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for biasing the final stages of a cascode amplifier, including:
(a) providing a cascode amplifier having at least two serially connected field effect transistor (FET) stages, each FET stage having a gate, a drain, and a source, the bottom FET stage having an input configured to be coupled to an RF input signal to be amplified, and the top FET stage of the cascode amplifier having an output for providing an amplified RF input signal;
(b) providing a cascode reference circuit having at least two serially connected FET stages, each FET having a gate, a drain, and a source, the gates of the bottom two FET stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two FET stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit; and
(c) providing an op-amp having a first and a second input and an output, the first input being coupled between a voltage source through a first resistor and a reference current source, the second input being coupled between the voltage source through a second resistor and the drain of the top FET stage of the cascode reference circuit, the output being coupled to the respective gates of the bottom FET stages of the cascode reference circuit and the cascode amplifier, wherein the op-amp is responsive to differences between its first and second inputs and outputs an adjustment gate bias voltage applied to the respective gates of the bottom FET stage of the cascode amplifier and of the cascode reference circuit that forces the mirror current in the cascode reference circuit to be approximately equal to a selected current value.