US 11,955,879 B2
Architecture to mitigate overshoot/undershoot in a voltage regulator
Venkatesh Wadeyar, Bangalore (IN); Vikas Lakhanpal, Bangalore (IN); and Preetam Charan Anand Tadeparthy, Bangalore (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Dec. 30, 2020, as Appl. No. 17/137,446.
Prior Publication US 2022/0209648 A1, Jun. 30, 2022
Int. Cl. G06F 1/28 (2006.01); H02M 1/32 (2007.01)
CPC H02M 1/32 (2013.01) [G06F 1/28 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A circuit comprising:
a controller, the controller including:
a converter configured to generate a first signal responsive to an input signal;
a summing block coupled to the converter, the summing block configured to receive the first signal and to generate a second signal;
a limiter coupled to the summing block and configured to generate a third signal responsive to the second signal and a code signal; and
a logic block configured to generate a target signal responsive to the third signal, wherein the target signal transitions from a current signal level to an intermediate level at a first slew rate in a first time period and then the target signal transitions from the intermediate level to a target signal level at a second slew rate in a second time period; and
a processor coupled to the controller, the processor configured to, responsive to the input signal, determine the first slew rate and the second slew rate, and provide the first slew rate and the second slew rate to the logic block.