US 11,955,778 B2
VCSEL binning for optical interconnects
Tali Septon, Haifa (IL); Itshak Kalifa, Bat-Yam (IL); Elad Mentovich, Tel Aviv (IL); Matan Galanty, Korzim (IL); Yaakov Gridish, Yoqneam Ilit (IL); Hanan Shumacher, Kohav Yair (IL); Vadim Balakhovski, Herzliya (IL); and Juan Jose Vegas Olmos, Solrød Strand (DK)
Assigned to MELLANOX TECHNOLOGIES, LTD., Yokneam (IL)
Filed by MELLANOX TECHNOLOGIES, LTD., Yokneam (IL)
Filed on Jan. 25, 2021, as Appl. No. 17/156,970.
Prior Publication US 2022/0239071 A1, Jul. 28, 2022
Int. Cl. H01S 5/183 (2006.01); H01S 5/00 (2006.01); H01S 5/026 (2006.01); H01S 5/42 (2006.01)
CPC H01S 5/423 (2013.01) [H01S 5/0014 (2013.01); H01S 5/0042 (2013.01); H01S 5/0261 (2013.01); H01S 5/18302 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for large scale Vertical-Cavity Surface-Emitting Laser (VCSEL) binning, comprising:
for at least a portion of VCSELs on a wafer, measuring a set of representative parameters of the VCSELs, of predetermined DC or small-signal values, and sorting the measured VCSELs into clusters according to the measured set of representative parameters of the VCSELs;
matching between an input impedance and an output impedance of the VCSELs and a VCSEL driver;
further sorting the clusters into sub-groups based on the matching to that comply with specifications of the VCSEL driver; and
providing a feedback signal to a Clock Data Recovery Unit (CDRU) for equalizing control signals provided to the VCSEL driver.