US 11,955,560 B2
Passivation layers for thin film transistors and methods of fabrication
Abhishek A. Sharma, Hillsboro, OR (US); Arnab Sen Gupta, Beaverton, OR (US); Travis W. LaJoie, Forest Grove, OR (US); Sarah Atanasov, Beaverton, OR (US); Chieh-Jen Ku, Hillsboro, OR (US); Bernhard Sell, Portland, OR (US); Noriyuki Sato, Hillsboro, OR (US); Van Le, Beaverton, OR (US); Matthew Metz, Portland, OR (US); Hui Jae Yoo, Hillsboro, OR (US); and Pei-Hua Wang, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 26, 2020, as Appl. No. 16/914,172.
Prior Publication US 2021/0408291 A1, Dec. 30, 2021
Int. Cl. H01L 29/66 (2006.01); H01L 27/22 (2006.01); H01L 29/786 (2006.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01)
CPC H01L 29/7869 (2013.01) [H01L 29/66969 (2013.01); H10B 61/22 (2023.02); H10B 63/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A thin film transistor (TFT) structure, comprising:
a gate electrode;
a gate dielectric layer on the gate electrode;
a channel layer on the gate dielectric layer, wherein the channel layer comprises a semiconductor material with a first polarity and comprising a first metal and oxygen;
a multi-layer material stack on the channel layer, opposite the gate dielectric layer;
a dielectric material over the multi-layer material stack and beyond a sidewall of the channel layer; and
source and drain contacts through the dielectric material, and in contact with the channel layer, wherein the multi-layer material stack comprises:
a first layer in contact with the channel layer,
wherein the first layer comprises a second metal absent from the channel layer, and wherein the first layer has a second polarity, complementary to the first polarity; and
a second layer in contact with the first layer, wherein the second layer and the dielectric material have different compositions.