US 11,955,536 B2
Semiconductor transistor structure and fabrication method thereof
Sheng-Hsu Liu, Changhua County (TW); Shih-Hsien Huang, Kaohsiung (TW); and Wen Yi Tan, Fujian (CN)
Assigned to United Semiconductor (Xiamen) Co., Ltd., Fujian (CN)
Filed by United Semiconductor (Xiamen) Co., Ltd., Fujian (CN)
Filed on Jul. 15, 2021, as Appl. No. 17/377,319.
Claims priority of application No. 202110651874.3 (CN), filed on Jun. 11, 2021.
Prior Publication US 2022/0399459 A1, Dec. 15, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/66795 (2013.01) [H01L 21/823431 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor transistor structure, comprising:
providing a substrate with a first conductivity type;
growing a fin structure on the substrate, the fin structure comprising an epitaxial stack disposed at an uppermost portion of the fin, the epitaxial stack comprising a first epitaxial SiGe layer having a second conductivity type opposite to the first conductivity type, a second epitaxial SiGe layer on the first epitaxial SiGe layer and in direct contact with the first epitaxial layer, and a third epitaxial SiGe layer having the second conductivity type on the second epitaxial SiGe layer and in direct contact with the second epitaxial SiGe layer, wherein the first epitaxial SiGe layer and the third epitaxial SiGe layer having the second conductivity type comprise a SiGe layer doped with phosphorus or arsenic, wherein the second epitaxial SiGe layer is an intrinsic SiGe layer;
forming a gate on the fin structure;
forming a buffer layer at a bottom of the fin structure; and
forming a strain relaxed layer on the buffer layer.