US 11,955,532 B2
Dual metal gate structure having portions of metal gate layers in contact with a gate dielectric
Jeffrey S. Leib, Beaverton, OR (US); Jenny Hu, Santa Clara, CA (US); Anindya Dasgupta, Portland, OR (US); Michael L. Hattendorf, Portland, OR (US); and Christopher P. Auth, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 26, 2020, as Appl. No. 17/080,713.
Application 16/908,468 is a division of application No. 15/859,356, filed on Dec. 30, 2017, granted, now 10,727,313, issued on Jul. 28, 2020.
Application 17/080,713 is a continuation of application No. 16/908,468, filed on Jun. 22, 2020, granted, now 10,854,732.
Claims priority of provisional application 62/593,149, filed on Nov. 30, 2017.
Prior Publication US 2021/0043754 A1, Feb. 11, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/033 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 27/02 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 29/167 (2006.01); H01L 29/417 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 49/02 (2006.01); H10B 10/00 (2023.01); H01L 23/00 (2006.01)
CPC H01L 29/66545 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02636 (2013.01); H01L 21/0337 (2013.01); H01L 21/28247 (2013.01); H01L 21/28518 (2013.01); H01L 21/28568 (2013.01); H01L 21/3086 (2013.01); H01L 21/31105 (2013.01); H01L 21/31144 (2013.01); H01L 21/76224 (2013.01); H01L 21/76232 (2013.01); H01L 21/76801 (2013.01); H01L 21/76802 (2013.01); H01L 21/76816 (2013.01); H01L 21/76834 (2013.01); H01L 21/76846 (2013.01); H01L 21/76849 (2013.01); H01L 21/76877 (2013.01); H01L 21/76897 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823842 (2013.01); H01L 21/823857 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 23/5283 (2013.01); H01L 23/53209 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 23/5329 (2013.01); H01L 27/0207 (2013.01); H01L 27/0886 (2013.01); H01L 27/0922 (2013.01); H01L 27/0924 (2013.01); H01L 28/20 (2013.01); H01L 28/24 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/167 (2013.01); H01L 29/41783 (2013.01); H01L 29/41791 (2013.01); H01L 29/516 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/66818 (2013.01); H01L 29/7843 (2013.01); H01L 29/7845 (2013.01); H01L 29/7846 (2013.01); H01L 29/7848 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01); H01L 29/7854 (2013.01); H10B 10/12 (2023.02); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/0332 (2013.01); H01L 21/76883 (2013.01); H01L 21/76885 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 29/665 (2013.01); H01L 29/7842 (2013.01); H01L 29/7853 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
an inter-layer dielectric layer having a trench therein, the trench having a sidewall;
a semiconductor substrate having a semiconductor fin protruding therefrom and extending into the trench in the inter-layer dielectric layer;
a trench isolation layer on the semiconductor substrate around a lower portion of the semiconductor fin, wherein an upper portion of the semiconductor fin extends above the trench isolation layer;
a gate dielectric over the upper portion of the semiconductor fin, the gate dielectric having a portion laterally spaced apart from the semiconductor fin and along the sidewall of the trench in the inter-layer dielectric layer;
a conductive layer over the gate dielectric, the conductive layer comprising titanium, nitrogen and oxygen, and a portion of the conductive layer in contact with the portion of the gate dielectric laterally spaced apart from the semiconductor fin;
a P-type metal gate layer over the conductive layer, the P-type metal gate layer having an uppermost surface above an uppermost surface of the conductive layer, and a portion of the P-type metal gate layer in contact with the portion of the gate dielectric laterally spaced apart from the semiconductor fin;
an N-type metal gate layer over the P-type metal gate layer, a portion of the N-type metal gate layer in contact with the portion of the gate dielectric laterally spaced apart from the semiconductor fin; and
a conductive fill over the N-type metal gate layer.
 
12. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
an inter-layer dielectric layer having a trench therein, the trench having a sidewall;
a semiconductor substrate having a semiconductor fin protruding therefrom and extending into the trench in the inter-layer dielectric layer;
a trench isolation layer on the semiconductor substrate around a lower portion of the semiconductor fin, wherein an upper portion of the semiconductor fin extends above the trench isolation layer;
a gate dielectric over the upper portion of the semiconductor fin, the gate dielectric having a portion laterally spaced apart from the semiconductor fin and along the sidewall of the trench in the inter-layer dielectric layer;
a conductive layer over the gate dielectric, the conductive layer comprising titanium, nitrogen and oxygen, and a portion of the conductive layer in contact with the portion of the gate dielectric laterally spaced apart from the semiconductor fin;
a P-type metal gate layer over the conductive layer, the P-type metal gate layer having an uppermost surface above an uppermost surface of the conductive layer, and a portion of the P-type metal gate layer in contact with the portion of the gate dielectric laterally spaced apart from the semiconductor fin;
an N-type metal gate layer over the P-type metal gate layer, a portion of the N-type metal gate layer in contact with the portion of the gate dielectric laterally spaced apart from the semiconductor fin; and
a conductive fill over the N-type metal gate layer.