US 11,955,529 B2
Semiconductor device with interlayer insulation structure including metal-organic framework layer and method of manufacturing the same
Won Tae Koo, Icheon-si (KR); and Jae Hyun Han, Icheon-si (KR)
Assigned to SK HYNIX INC., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Dec. 6, 2021, as Appl. No. 17/543,097.
Claims priority of application No. 10-2021-0091873 (KR), filed on Jul. 13, 2021.
Prior Publication US 2023/0013343 A1, Jan. 19, 2023
Int. Cl. H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01)
CPC H01L 29/516 (2013.01) [H01L 29/40111 (2019.08); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/42324 (2013.01); H01L 29/4234 (2013.01); H01L 29/518 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 51/10 (2023.02); H10B 51/20 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device comprising;
a substrate;
a gate structure disposed over the substrate, the gate structure including gate electrode layers and interlayer insulation structures that are alternately stacked with each other;
a dielectric structure disposed over the substrate to contact a sidewall surface of the gate structure; and
a channel layer disposed on a sidewall surface of the dielectric structure over the substrate,
wherein each of the interlayer insulation structures includes an insulation layer and a metal-organic framework layer that are disposed on the same plane,
wherein the insulation layer and the metal-organic framework layer contact portions of the gate electrode layer, respectively.